1. Field
The example embodiments relate to a reading level, and more particularly, to a method and apparatus for controlling a reading level of a memory cell which may reduce data reading errors when reading a flash memory cell.
2. Description of Related Art
In a flash memory device, the critical voltage of a memory cell and a predetermined or given reading level may be compared, and data programmed in the memory cell may be read based on the critical voltage and the reading level.
As an example, in a memory cell of a four-bit, Multi Level Cell (MLC) method, the critical voltage of a memory cell may be compared to minimum fifteen predetermined or given reading levels to read data programmed in the memory cell.
However, when data reading errors for data read by a reading level increase, the error control code (ECC) decoding level, which may correct data reading errors, may need to be improved. Consequently, latency of a reading operation increases and the cost for an ECC decoder increase.
Additionally, the lifetime of apparatus and retention of stored data may be degraded due to the error increase.
A method and apparatus for controlling a reading level of a memory cell may address these issues.